1. Field of the Invention
The present invention relates to an input/output buffer circuit in a semiconductor integrated circuit and, more particularly, to an input/output buffer circuit which allows input/output interfacing with a device designed to be operated on a different supply voltage.
2. Description of the Related Art
FIG. 1 shows an input/output buffer circuit using, e.g., a CMOS FET (complementary metal oxide semiconductor field-effect transistor), which is arranged in a conventional semiconductor integrated circuit. Referring to FIG. 1, reference numeral 11 denotes an input/output pad; and 12 and 13, input and output buffer circuits which commonly use the input/output pad 11. The output buffer circuit 13 has a p-channel MOS transistor (PMOS transistor) QP1 and an n-channel MOS transistor (NMOS transistor) QN1 which are connected in series between a supply potential (Vcc) node and a ground potential (Vss) node. The output buffer circuit 13 outputs an output signal Dout from a circuit in the integrated circuit to the input/output pad 11 when an output enable signal EN is activated. In the input buffer circuit 12, a CMOS inverter constituted by a PMOS transistor QP2 and an NMOS transistor QN2 is used as an input stage. The input buffer circuit 12 inputs a signal, received from the outside of the integrated circuit, through the input/output pad 11, as an internal input signal Din, to a circuit in the integrated circuit.
When the above-described input and output buffer circuits are to be used as an output buffer, if the output enable signal EN is set at "H" level, a signal of "H"/"L" level is output to the input/output pad 11 in accordance with the "H"/"L" level of the output signal Dout. When the input and output buffer circuits are to be used as an input buffer, if the output enable signal EN is set at "L" level, a gate node N1 of the PMOS transistor QP1 and a gate node N2 of the MNOS transistor QN1 are accordingly set at "H"/"L" level. An input/output node N3 is set in a high impedance state, and a signal is input from the input/output pad 11 to the input stage inverter through the input/output node N3. Finally, the internal input signal Din is input to a circuit in the integrated circuit.
FIG. 2 shows the sectional structures of the PMOS transistor QP1 and the NMOS transistor QN1 in FIG. 1. Referring to FIG. 2, reference numeral 21 denotes a p-type semiconductor substrate; 22, an n-type well; 23, a p-type impurity region formed in the n-type well 22 and serving as the source/drain of the PMOS transistor QP1; 24, an n-type impurity region for electrode extraction formed in the n-type well 22; 25, a p-type well; 26, an n-type impurity region formed in the p-type well 25 and serving as the source/drain of the NMOS transistor QN1; 27, a p-type impurity region for electrode extraction formed in the p-type well; 29, a gate electrode for the PMOS transistor QP1; 30, a source line for the PMOS transistor QP1; 31, a gate electrode for the NMOS transistor QN1; 32, a source line for the NMOS transistor QN1; and 33, a drain line for the PMOS transistor QP1 and the NMOS transistor QN1.
With advances in micropatterning of elements, the supply voltage of a device itself must be decreased in terms of reliability. The supply voltage is increasingly shifted from 5 V to 3.3 V. Especially in recent microprocessors and the like, it is expected that the supply voltage will be shifted to 3.3 V. Even if the supply voltage of a given integrated circuit is set to be 3.3 V, other devices (peripheral logic circuits and memories) with which the integrated circuit interfaces may be operated at 5 V. In this case, 5 V is applied, as an input potential, to the input/output node N3 in the above-described input/output buffer circuit arranged in the integrated circuit. In such a case, since the potential of the n-type well 22 is 3.3 V, the pn junction (at portion A in FIG. 2,) between the p-type impurity region 23 to which the input potential of 5 V is applied, and the n-type well 22, is forward-biased. As a result, interfacing cannot be performed. In addition, the input voltage of 5 V is applied to the gates of the PMOS and NMOS transistors QP2 and QN2 of the input-stage inverter, posing problems in terms of reliability.
In order to solve the problem due to the phenomenon that the pn junction between the p-type impurity region and the n-type well is forward-biased in a signal input mode, as described above, an input/output buffer circuit shown in FIG. 3 is disclosed in Randy Allmon et al., "System, Process, and Design Implication of a Reduced Supply voltage Microprocessor", ISSCC 90, pp. 48. FIG. 3 shows only circuits associated with the solution to the above-described problem, with various control circuits omitted. Note that 3.3 V and 5 V are respectively used as first and second supply potentials Vcc1 and Vcc2.
Referring to FIG. 3, a substrate (n-type well) in which an output PMOS transistor QP3 having a large channel width is formed is connected to the potential Vcc2 (=5 V). In order to transfer the potential of an input/output node N4 to a gate node N3 of the PMOS transistor QP3 and finally raise the potential to the potential Vcc2 (=5 V) in a signal input mode, a PMOS transistor QP2, having a gate connected to the potential Vcc1 (=3.3 V), is inserted between the nodes N3 and N4. In addition, in order to transfer the potential Vcc1 (=3.3 V) of the drain node N2 of a PMOS transistor QP1 to the gate node N3 and reliably turn off the output PMOS transistor QP3 when the PMOS transistor QP1 is turned on in the signal output mode, an NMOS transistor QN2 having a gate connected to the potential Vcc2 (=5 V) is inserted between the nodes N2 and N3.
FIG. 4 shows the sectional structure of the PMOS transistor QP3 in FIG. 3. Referring to FIG. 4, reference numeral 21 denotes a p-type semiconductor substrate; 22, an n-type well; 23, a p-type impurity region formed in the n-type well 22 and serving as a source/drain region; 24, a n-type impurity region for electrode extraction formed in the n-type well 22; 28, a gate insulating film on the substrate surface.
According to the circuit shown in FIG. 3, the output PMOS transistor QP3 is connected to the potential Vcc2 (=5 V). Even if a 5-V signal is input to the input/output node N4, the pn junction (a portion B in FIG. 4) between the p-type impurity region 23 and the n-type well 22 is not forward-biased. Therefore, input/output interfacing with other devices can be performed. FIG. 5 shows the waveforms of voltages at the nodes N2, N3, and N4 in a signal input state. More specifically, input of a 5-V signal to the input/output node N4 is started at time t1, and the potential of the node N4 exceeds the potential Vcc1 (=3.3 V) at time t2. When the potential exceeds a potential of Vcc1+Vtp (the threshold voltage of the PMOS transistor QP2) at time t3, the potential of the gate node N3 of the PMOS transistor QP3 rises with an increase in potential of the node N4 and finally reaches the potential Vcc2 (=5 V). As a result, the output PMOS transistor QP3 is completely turned OFF, thus preventing a large input leakage current from flowing from the node N4 to the first supply potential Vcc1 through the PMOS transistor QP3.
The following problems are posed with respect to the transistors QP1, QN1, and QN2 arranged in a circuit portion I, shown in FIG. 3. The NMOS transistor QN2 serves to transfer the potential of the node N3 to the node N2 in a signal input mode. Similar to the output PMOS transistor QP3, the PMOS transistor QP1 is designed such that the potential Vcc2 (=5 V) is connected to the substrate (n-type well) to prevent forward bias in the signal input mode. However, as shown in the timing chart in FIG. 5, since the potential of the node N2 may become Vcc1.+-..alpha. depending on the transistor characteristics (e.g., a back bias effect) of the NMOS transistor QN2, the PMOS transistor QP1 is kept ON during the signal input period. For this reason, an input leakage due to an ON current is present. Although it is expected that this input leakage current is about 1 to 2 mA, in an integrated circuit such as a microprocessor having 100 or more input/output pads, the input leakage current will exceed 100 mA, posing a serious problem.
Furthermore, in the circuit shown in FIG. 3, since an input potential of a 5-V level is applied to the output NMOS transistor QN3, the transistors QP1, QN1, and QN2 in the circuit portion I, and the input-stage inverter (not shown) of the input buffer circuit, a problem is also posed in terms of reliability.
As described above, when the conventional input/output buffer circuit is to be connected to another device, if the other device is designed to output a signal having a voltage level (e.g., 5 V) higher than the supply voltage (e.g., 3.3 V) of the integrated circuit incorporating this input/output buffer circuit, connection to the other device cannot be allowed, i.e., input/output interfacing with the other device cannot be performed, or an input leakage current path is undesirably formed.
It is an object of the present invention to provide an input/output buffer circuit which allows input/output interfacing with another device designed to output a signal having a voltage level higher than the supply voltage of an integrated circuit incorporating the input/output buffer circuit.